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Inthesedays,everynewlyaddedhardwarefeaturemustnotchangetheunderlying instruction set architecture (ISA), in order to avoid adaptation or recompilation of existing code. Nevertheless, this need for compatibility imposes a great number of restrictions to the designers, because it keeps them tied to a specific ISA and all its legacy hardware issues. Considering that the market is mainly dominated by three different ISAs (and, very likely, more to come): ×86, used in the general purpose field; ARM, used in embedded systems, andPowerPCwhichcoversawidegamutofsolutions,theneedforanotherlevel(attheISA) of adaptability is evident. Binary translation (BT) appears as a solution for that, since it is capable of transforming binary code so it can be executed on another target architecture. However,BTaddsanotherlayerbetweencodeandactualexecution,thereforebringinghuge performance penalties. To overcome this drawback, we propose a new mechanism based on a dynamic two-level binary translation system. The first level can translate from multiple architectures into an intermediate-level code, which will be optimized by the second level forexecutiononadynamicreconfigurablearray.Inthisway,thedesignercantakeadvantage of a BT system and program for multiple fields of application, without worrying about the underlying architecture. We present three case studies, along with a discussion as to how the first BT level is easily expandable to other ISAs.