VLSIcircuitsareperceivedtodissipateextrapowerduringtestingwhencompared with that of the normal function. Drastic heat may reduce circuit consistency, shoot up packagecost,andevencausepermanentdamagetothecircuitundertest.Thusminimization of test power has gained increased significance. This paper explores the avenues in power minimizationduringtestapplicationinCMOSVLSIcircuitssincepowerconsumptionduring testing is high when compared to normal operation. Design of low transition Test Pattern Generators is one usual method adopted to reduce power consumption. In the Proposed ModifiedLowTransitionLinearFeedbackShiftRegister,powerdissipationduringtestingis reduced by minimizing the switching activity between successive test vectors by comparing thetwoconsecutivetestvectorsandinsertingrandombitsuchthattotalnumberoftransitions isreducedwithoutaffectingtherandomness.Significantadvantageofthismethodisreduced power consumption with reduced complexity when compared to other existing methods. Considering experimental results there is a significant reduction in power consumption up to 36.2% for ISCAS’85 combinational bench mark circuits and up to 10% for ISCAS’89 Benchmark sequential circuit with marginal increase in area overhead.

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• An improved low transition test pattern generator for low power applications